1. Field of the Invention
The present invention relates to a semiconductor memory device and a testing method thereof. Particularly, the present invention relates to a semiconductor memory device operating in synchronization with a clock signal, having a test mode to test whether each memory cell is proper or not, and a testing method thereof.
2. Description of the Background Art
Semiconductor memory devices such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are conventionally subjected to testing prior to shipment to determine whether each memory cell is proper or not. This testing includes the steps of writing predetermined data into each of a plurality of memory cells included in the memory array, and reading out data from each memory cell. Determination is made that a memory cell is proper when the logic of data read out from that memory cell matches the logic of the data read into that memory cell. A memory cell is determined to be defective when such logics of data do not match. A defective memory cell is replaced with a spare memory cell.
Some testing methods conduct writing of external data into a memory cell and reading out data from another memory cell concurrently (for example, refer to Japanese Patent Laying-Open No. 59-175100).
In the conventional testing method, a data signal is written after an address signal and the data signal are applied to the semiconductor memory device from a tester, and a data signal is read out after an address signal is applied to the semiconductor memory device from the tester. There was a disadvantage that the testing operation is complex.